With the development of the semiconductor industry, three-dimensional (3D) semiconductor devices (e.g., 3D NAND memory devices) are widely explored. However, the structures of the 3D semiconductor devices that include multiple stacked tiers (e.g., layers) and high aspect ratio openings (e.g., holes) extending into the tiers, as well as the techniques of fabricating such 3D semiconductor devices, may present some implementation challenges.